In general, a CMOS inverter circuit comprises a series of complementary component MOS field effect transistors and one of the component transistors is nonconductive in either logic state. Then, a small amount of leakage current flows in either steady state and , for this reason, the low power consumption is the most attractive feature of the CMOS inverter circuit but the CMOS inverter circuit suffers from a limited switching speed. On the other hand, a bipolar transistor can drive a capacitive load with much less speed degradation but consumes a large amount of power. In short, there is a trade-off between power and speed. A particular attention is being paid to bi-CMOS circuits as a compromise between power and speed.
A typical example of the bi-CMOS circuit is illustrated in FIG. 1 of the drawings. The bi-CMOS circuit illustrated in FIG. 1 serves as a buffer circuit and comprises a CMOS inverter circuit 1 consisting of a p-channel type MOS field-effect transistor 2 and an n-channel type MOS field-effect transistor 3, a source follower circuit 4 consisting of an n-channel type MOS field-effect transistor 5 and a resistor 6, and a series combination of n-p-n bipolar transistors 7 and 8 coupled between a source of positive voltage 9 of 5.0 volt and a ground terminal. The CMOS inverter circuit 1 is also coupled between the source of positive voltage 9 and the ground terminal and has a common drain node 10 which is coupled to the base electrode of the n-p-n bipolar transistor 7. The source follower circuit 4 is coupled between the collector electrode of the n-p-n bipolar transistor 8 and the ground terminal and has an output node 11 coupled to the base electrode of the n-p-n bipolar transistor 8. The buffer circuit illustrated in FIG. 1 further has an input terminal 12 connected in parallel to the respective gate electrodes of the MOS filled-effect transistors 2, 3 and 5 so that the CMOS inverter circuit 1 shifts the n-p-n bipolar transistor 7 between on and off states to produce an output signal of high or low voltage level at an output node 13 depending upon the voltage level of the input node 12, and, on the other hand, the source follower circuit 4 drives the n-p-n bipolar transistor 8 so as to cause the output node 13 to rapidly go down to the low voltage level. In this example, when a certain forward-biased voltage V.sub.EB ranging between 0.6 volt and 0.8 volt is applied to the emitterbase junction of the bipolar transistor 7, the bipolar transistor 7 turns on to provide a current path from the source of positive voltage 9 to the output node 13. Similarly, the n-p-n bipolar transistor 8 turns on to provide a current path from the output node 13 to the ground when the certain forward-biased voltage is applied to the emitter-base junction thereof. The output node 13 is coupled to a CMOS inverter circuit 14 of the subsequent stage consisting of a p-channel type MOS field-effect transistor 15 and an n-channel type MOS field-effect transistor 16 so that the n-p-n bipolar transistors 7 and 8 drives the CMOS inverter circuit 14 of the subsequent stage. The p-channel type MOS field-effect transistor 15 has a certain threshold voltage V.sub.TH ranging between -0.5 volt and 0.8 volt, then the MOS field-effect transistor 15 turns on when a certain positive voltage level ranging between 4.2 volt and 4.5 volt appears at the output node 13. The n-channel type MOS field-effect transistor 16 has a certain threshold voltage ranging between 0.5 volt and 0.8 volt, then the MOS field-effect transistor 16 is turned on if the output node 13 has a positive voltage level higher than the threshold voltage of the MOS field-effect-transistor 16.
Another example of the prior-art bi-CMOS circuit is illustrated in FIG. 2. The bi-CMOS circuit illustrated in FIG. 2 also serves as a buffer circuit and comprises a 2-input NAND gate 21 consisting of p-channel type MOS field-effect transistors 22 and 23 coupled in parallel between a source of positive voltage level 24 and an output node 25 thereof and a series combination of n-channel type MOS field-effect transistors 26 and 27 coupled between the output node 25 and a ground terminal, a source follower circuit 28 consisting of a series combination of two n-channel type MOS field-effect transistors 29 and 30 and a resistor 31, and a series combination of n-p-n bipolar transistors 32 and 33 coupled between the source of positive voltage level 24 and the ground terminal. The output node 25 is coupled to the base electrode of the n-p-n bipolar transistor 32 and an output node 34 of the source follower circuit 28 is connected to the base electrode of the n-p-n bipolar transistor 33. Between the n-p-n bipolar transistors 32 and 33 is provided an output node 35 of the buffer circuit which supplies a current to a capacitive load CL of the subsequent stage. The capacitive load CL is usually formed by parasitic gate capacitances of MOS field-effect transistors forming the subsequent stages. The 2-input NAND gate 21 and the source follower circuit 28 are coupled in parallel to input nodes 36 and 37 so that the n-p-n bipolar transistor 32 is shifted between on and off states depending upon the voltage levels of the input nodes 36 and 37. In thermal equilibrium condition, each of the bipolar transistors 32 and 33 has a built-in potential of the emitter-base junction approximately equal to that of the bipolar transistor 7 or 8, and each of the MOS field-effect transistors forming part of the subsequent stage also has a threshold voltage approximately equal to that of the MOS field-effect transistor 15 or 16. A modification of the buffer circuit illustrated in FIG. 2 is disclosed by H. Higuchi et al in "PERFORMANCE AND STRUCTURE OF SCALED-DOWN BIPOLAR DEVICES MERGED WITH CMOSFETS", IEDM 84, 694-697. In the modification disclosed in the above paper the resistor 31 is replaced by a MOS field-effect transistor provided with a gate electrode connected to the output node of a 2-input NAND gate corresponding to the NAND gate 21.
A problem has been encountered in the buffer circuits illustrated in FIGS. 1 and 2 and the modification in a high through current or a leakage current caused by simultaneous on states of the MOS field-effect transistors forming the subsequent stage. Focusing on the buffer circuit illustrated in FIG. 1, the problem inherent in the prior-art buffer circuits will be hereinunder described in detail.
When the input terminal 12 has a certain positive high voltage level, the n-channel type MOS field-effect transistors 3 and 5 are turned on but the p-channel type MOS field-effect transistor 1 is turned off, so that the output nodes 10 and 11 have a certainlow voltage level. This results in that both of the n-p-n bipolar transistors 7 and 8 remain in the off states, respectively. The parasitic gate capacitance CL coupled to the output node 13 has been sufficiently discharged so that a low voltage level approximately equal to the ground level appears at the output node 13. With the low voltage level approximately equal to the ground level, a current path is provided from the source of positive voltage level 9 to an output node of the CMOS inverter circuit 14 by turning the MOS field-effect transistor 15 on and turning the MOS field-effect transistor 16 off, thereby producing an output signal of a certain high voltage level.
However, when the input terminal 12 goes down to a certain low voltage level, the n-channel type MOS field-effect transistors 3 and 5 turn off and, on the other hand, the p-channel type MOS field-effect transistor 2 turns on. These switching operations cause the output node 10 to go up toward a certain high voltage level, but the output node 11 remains in the low voltage level to keep the n-p-n bipolar transistor 8 off. With the certain positive voltage level appearing at the output node 10, the n-p-n bipolar transistor 7 turns on to supply a current to the output node 13, then the parasitic gate capacitance CL is fully accumulated. When the parasitic gate capacitance CL is fully accumulated, the output node 13 reaches the certain positive voltage level lower than the source of positive voltage level of 5.0 volt by the emitter-base voltage V.sub.EB. The emitter-base voltage V.sub.EB is selected to have a value ranging between 0.6 volt and 0.8 volt so that the certain positive voltage level has a value ranging between 4.2 volt and 4.4 volt. The output node 13 is high enough to cause the n-channel type MOS field-effect transistor 16 to turn on. However, a difference voltage ranging between 0.6 volt and 0.8 volt takes place between the source of positive voltage 9 and the output node 13 when the n-channel MOS field-effect transistor 16 begins to turn on. As described hereinbefore, the p-channel type MOS field-effect transistor 15 has the threshold voltage ranging between -0.5 volt and -0.8 volt so that the p-channel MOS field-effect transistor 15 momentary remains in the on state. The simultaneous on states of the MOS field-effect transistors 15 and 16 allow the through current to flow from the source of positive voltage level 9 to the ground terminal. The p-channel type MOS field-effect transistor 15 is turned on for a while and goes to the off state to cut off the current path. On the other hand, when the input terminal 12 goes up to the certain positive voltage level again, the n-channel type MOS field effect transistors 3 and 5 turn on and the p-channel type MOS field-effect transistor 2 turns off. Then, the output node 10 goes down toward the ground level and the n-p-n bipolar transistor 7 turns off to cut off the current path from the source of positive voltage 9 to the output node 13. As the n-channel type MOS field-effect transistor 5 provides a current path from the output node 13 to the ground terminal, the parasitic gate capacitance CL is discharged therethrough. This results in increasing in voltage level at the output node 11. When the voltage level at the output node 11 reaches the emitter-base voltage V.sub.EB of the n-p-n bipolar transistor 8, the n-p-n bipolar transistor 8 turns on to rapidly discharge the parasitic gate capacitance CL. During the discharge of the parasitic capacitance CL, the output node 13 is clamped at a voltage level approximately equal to the emitter-base voltage level V.sub.EB with respect to the ground level. Then, the n-channel type field-effect transistor 16 remains in the on state. As the p-channel type MOS field-effect transistor 15 has already turned on, a current path is established between the source of positive voltage 9 and the ground terminal and the through current flows. After the discharge of the parasitic gate capacitance CL the n-channel type MOS field-effect transistor 16 turns off to cut off the current path. This results in increasing in power consumption.
It is therefore an important object of the present invention to provide a buffer circuit which is substantially free from the through current or leakage current.